CY7C1461AV25 Datasheet - Cypress Semiconductor

CY7C1461AV25 Flow-Through SRAM

1] The CY7C1461AV25/CY7C1463AV25/CY7C1465AV25 are 2.5V, 1M × 36/2M × 18/512K × 72 Synchronous Flow-through Burst SRAMs designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV25/CY7C1463AV25/ CY7C1465AV25 is equipped with.

CY7C1461AV25 Features

* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

* Can support up to 133-MHz bus operations with zero wait states

* Data is transferred on every clock

* Pin-compatible and functionally equivalent to ZBT™ devices

* Int

CY7C1461AV25_CypressSemiconductor.pdf