CY7C1511JV18 Datasheet - Cypress Semiconductor

CY7C1511JV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture

The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support.

CY7C1511JV18 Features

* Configurations CY7C1511JV18

* 8M x 8 CY7C1526JV18

* 8M x 9 CY7C1513JV18

* 4M x 18 CY7C1515JV18

* 2M x 36 Separate independent read and write data ports

* Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bu

CY7C1511JV18_CypressSemiconductor.pdf