CY7C1511V18 Datasheet - Cypress Semiconductor

CY7C1511V18 - (CY7C15xxV18) SRAM 4-Word Burst Architecture

The CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port ha.

CY7C1511V18 Features

* Separate Independent Read and Write Data Ports

* Supports concurrent transactions

* 250-MHz Clock for High Bandwidth

* 4-Word Burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 M

CY7C1511V18_CypressSemiconductor.pdf