CY7C1512AV18, CY7C1510AV18 Datasheet - Cypress Semiconductor

CY7C1512AV18 - 72-Mbit QDR-II SRAM 2-Word Burst Architecture

Maximum Operating Frequency Maximum Operating Current x8 x9 x18 x36 250 MHz 250 1230 1240 1350 1560 Configurations CY7C1510AV18 * 8M x 8 CY7C1525AV18 * 8M x 9 CY7C1512AV18 * 4M x 18 CY7C1514AV18 * 2M x 36 Functional Description The CY7C1510AV18, CY7C1525AV18,

CY7C1512AV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 250 MHz clock for high bandwidth

* 2-word burst on all accesses

* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz

* Two input clocks (

CY7C1510AV18_CypressSemiconductor.pdf