CY7C1512KV18 Datasheet - Cypress Semiconductor

CY7C1512KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture

CY7C1512KV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 350 MHz clock for high bandwidth

* Two-word burst on all accesses

* Double data rate (DDR) interfaces on both read and write ports (data transferred at 700 MHz) at 350 MHz

* Two input clocks

Datasheet Details

CY7C1512KV18

Cypress Semiconductor

620.47 KB

72-mbit qdr ii sram two-word burst architecture.

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