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CY7C1524KV18 - 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture

This page provides the datasheet information for the CY7C1524KV18, a member of the CY7C1522KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture family.

Datasheet Summary

Description

The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and CY7C1524KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (Double Data Rate Separate I/O) architecture.

The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Functional.

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Datasheet Details

Part number CY7C1524KV18
Manufacturer Cypress Semiconductor
File Size 906.43 KB
Description 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
Datasheet download datasheet CY7C1524KV18 Datasheet
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Full PDF Text Transcription

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CY7C1522KV18, CY7C1529KV18 CY7C1523KV18, CY7C1524KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1522KV18, CY7C1529KV18, CY7C1523KV18, and CY7C1524KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (Double Data Rate Separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus required with common I/O devices.
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