* ISSUE DEFINITION If the input clock (K Clock) is left floating when the device is in JTAG mode, spurious high frequency noise on this input can be interpreted by the device as valid clocks. This could cause the impedance matchi
CY7C152xV18 Datasheet (279.66 KB)
CY7C152xV18
Cypress Semiconductor
279.66 KB
(cy7c1xxxxvxx) ram9 qdr-i/ddr-i/qdr-ii/ddr- ii errata.
CY7C129 DV18/CY7C130 DV25 CY7C130 BV18/CY7C130 BV25/CY7C132 BV25 CY7C131 BV18 / CY7C132 BV18/CY7C139 BV18 CY7C191 .
📁 Related Datasheet
CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture (Cypress Semiconductor)
CY7C1520V18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)
CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture (Cypress Semiconductor)
CY7C1521V18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)
CY7C1522AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture (Cypress Semiconductor)
CY7C1522JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture (Cypress Semiconductor)
CY7C1522KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture (Cypress Semiconductor)
CY7C1522V18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture (Cypress Semiconductor)
CY7C1523AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture (Cypress Semiconductor)
CY7C1523JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture (Cypress Semiconductor)
TAGS
Image Gallery
