* 144-Mbit density (8 M × 18, 4 M × 36)
* 550-MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5-clock cycle latency
* Two input clocks (K and K) for
CY7C1670KV18 Datasheet (590.51 KB)
CY7C1670KV18
Cypress Semiconductor
590.51 KB
144-mbit ddr ii+ sram two-word burst architecture.
CY7C1668KV18 CY7C1670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 144-Mbit DDR II+ SRAM Two-Word Burst Architectur.
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