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CY7C1312KV18 18-Mbit QDR II SRAM Two-Word Burst Architecture

CY7C1312KV18 Description

CY7C1312KV18/CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 18-Mbit QDR® II SRAM Two-Word Burst Architecture .
The CY7C1312KV18, and CY7C1314KV18 are 1.

CY7C1312KV18 Features

* Separate independent read and write data ports
* Supports concurrent transactions
* 333 MHz clock for high bandwidth
* Two-word burst on all accesses
* Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
* Two input clocks

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Datasheet Details

Part number
CY7C1312KV18
Manufacturer
Cypress Semiconductor
File Size
790.78 KB
Datasheet
CY7C1312KV18-CypressSemiconductor.pdf
Description
18-Mbit QDR II SRAM Two-Word Burst Architecture

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📌 All Tags

18-Mbit QDR SRAM Two-Word Burst Architecture Cypress Semiconductor
Cypress Semiconductor CY7C1312KV18-like datasheet