FDG6320C Datasheet - Fairchild Semiconductor

FDG6320C Dual N & P Channel Digital FET

These dual N & P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low volta.

FDG6320C Features

* N-Ch 0.22 A, 25 V, RDS(ON) = 4.0 Ω @ VGS= 4.5 V, RDS(ON) = 5.0 Ω @ VGS= 2.7 V. P-Ch -0.14 A, -25V, RDS(ON) = 10 Ω @ VGS= -4.5V, RDS(ON) = 13 Ω @ VGS= -2.7V. Very small package outline SC70-6. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Sou

FDG6320C Datasheet (196.28 KB)