ZL30161 - Network Synchronization Clock Translator
All device inputs and outputs are LVCMOS unless it is specifically stated to be differential.
For the I/O column, there are digital inputs (I), digital outputs (O), analog inputs (A-I) and analog outputs (A-O).
Ball # Name Input Reference M3 ref0_p M4 ref0_n L3 ref1_p L4 ref1_n M5 ref2_
ZL30161 Features
* Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL)
* Programmable DPLL/Numerically Controlled Oscillators (NCO)
* Synchronizes to any clock rate from 1 Hz to 750 MHz
* Three programmable synthesizers generate any c
