ZL30168 Datasheet - Microsemi

ZL30168 Enhanced Quad Clock Translator

Precise Frequency Monitor (PFM) Guard Soak Timer (GST) Figure 14 "Typical Power-Up Reset and Configuration Circuit" 5.1, “ZL30168 Configuration programming“ Register Name: phasemem_limit_ref0 127 Register Name: dpll0_df_offset 187 13.0, “Package Markings“ Change Updated GPIO[5:6] power-up setting.

ZL30168 Features

* Four independent clock channels

* Programmable synthesizers generate any clockrate from 1 Hz to 750 MHz

* Four precision synthesizers generate clocks with maximum jitter below 0.63 ps RMS

* Four programmable digital PLLs/Numerically Controlled Oscillators (NCOs)/OTN

ZL30168 Datasheet (725.32 KB)