ZL30163 - Network Synchronization Clock Translator
2 Microsemi Corporation ZL30163 Short Form Data Sheet 2.0 Pin Description All device inputs and outputs are LVCMOS unless it is specifically stated to be differential.
For the I/O column, there are digital inputs (I), digital outputs (O), analog inputs (A-I) and analog outputs (A-O).
Ball # Na
ZL30163 Features
* Fully compliant SEC (G.813) and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL)
* Two programmable DPLLs/Numerically Controlled Oscillators (NCOs) synchronize to any clock rate from 1 Hz to 750 MHz
* Four programmable synthesizers generate any clock r
