PLL601-02 - Low Phase Noise PLL Clock Multiplier

PhaseLink

Datasheet Details

Part number	PLL601-02
Manufacturer	PhaseLink
File Size	75.43 KB
Description	Low Phase Noise PLL Clock Multiplier
Datasheet	PLL601-02_PhaseLink.pdf

The PLL601-02 is a low cost, high performance and low phase noise clock synthesizer.

w.
w w Full swing CMOS outputs with 25 mA drive capability at TTL levels. Reference 10-27MHz crystal or clock. Integrated crystal load capacitor: no external load capacitor required. Output clocks up to 160MHz at 3.3V. Low phase noise (-126dBc/Hz @ 1kHz). Output Enable function. Low jitter (RMS): 6.4ps (period), 9.4ps (accum. ) Advanced low power sub-micron CMOS process. 3.3V operation. Availab.

📁 PLL601-02 Similar Datasheet

PLL0210A - PHASE LOCKED LOOP (Z-Communications)
PLL0930A - PHASE LOCKED LOOP (Z-Communications)
PLL1000A - PHASE LOCKED LOOP (Z-Communications)
PLL102-03 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-04 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-05 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-10 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-108 - Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)

Other Datasheets by PhaseLink

Published: Feb 10, 2006 |