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TC58NS100DC - 1 GBit CMOS NAND EPROM

Datasheet Summary

Description

The TC58NS100 is a single 3.3-V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks.

Features

  • Organization Memory cell array 528 × 256K × 8 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read Mode control Serial input/output, Command control Complies with the SmartMediaTM Electrical Specification and Data Format Specification issued by the SSFDC Forum.
  • Power supply VCC = 3.3 V ± 0.3 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array-register 2.

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Datasheet Details

Part number TC58NS100DC
Manufacturer Toshiba
File Size 526.45 KB
Description 1 GBit CMOS NAND EPROM
Datasheet download datasheet TC58NS100DC Datasheet
Additional preview pages of the TC58NS100DC datasheet.

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Full PDF Text Transcription

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TC58NS100DC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 TM 1-GBIT (128M × 8 BITS) CMOS NAND E PROM (128M BYTE SmartMedia DESCRIPTION ) The TC58NS100 is a single 3.3-V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages). The TC58NS100 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.
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