CY7C1261V18 - 1.8V Synchronous Pipelined SRAM

Cypress Semiconductor

Datasheet Details

Separate independent read and write data ports.
Supports concurrent transactions.
300 MHz to 400 MHz clock for high bandwidth.
4-Word Burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 400 MHz.
Read latency of 2.5 clock cycles.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed.

📁 CY7C1261V18 Similar Datasheet

CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)

Other Datasheets by Cypress Semiconductor

Published: Nov 6, 2016 |