CY7C1264XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
CY7C1264XV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 450 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
