CY7C1263KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Separate independent read and write data ports.
Supports concurrent transactions.
550 MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) Interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed sy.

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Published: Mar 14, 2017 |