* Separate Independent Read and Write Data Ports
* Supports concurrent transactions
* 633 MHz Clock for High Bandwidth
* Four-word Burst for Reducing Address Bus Frequency
* Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz
CY7C1263XV18 Datasheet (1.17 MB)
CY7C1263XV18
Cypress Semiconductor
1.17 MB
36-mbit qdr ii+ xtreme sram four-word burst architecture.
CY7C1263XV18 CY7C1265XV18 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ Xtreme SRAM Four-Word B.
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