CY7C1262XV18 Datasheet - Cypress Semiconductor

CY7C1262XV18 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

CY7C1262XV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 450 MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz

Datasheet Details

CY7C1262XV18

Cypress Semiconductor

1.04 MB

36-mbit qdr ii+ xtreme sram two-word burst architecture.

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