CY7C1265V18 Datasheet - Cypress Semiconductor

1.8V Synchronous Pipelined SRAM

* Separate independent read and write data ports

* Supports concurrent transactions

* 300 MHz to 400 MHz clock for high bandwidth

* 4-Word Burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 40

CY7C1265V18

Cypress Semiconductor

404.82 KB

1.8v synchronous pipelined sram.

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