CY7C1265V18 - 1.8V Synchronous Pipelined SRAM
CY7C1265V18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 300 MHz to 400 MHz clock for high bandwidth
* 4-Word Burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 800 MHz) at 40
