CY7C1265XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
CY7C1265XV18 Features
* Separate Independent Read and Write Data Ports
* Supports concurrent transactions
* 633 MHz Clock for High Bandwidth
* Four-word Burst for Reducing Address Bus Frequency
* Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz
