CY7C1265XV18, CY7C1263XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Part number	CY7C1265XV18, CY7C1263XV18
Manufacturer	Cypress Semiconductor
File Size	1.17 MB
Description	36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
Datasheet	CY7C1263XV18-CypressSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: CY7C1265XV18, CY7C1263XV18. Please refer to the document for exact specifications by model.

Separate Independent Read and Write Data Ports.
Supports concurrent transactions.
633 MHz Clock for High Bandwidth.
Four-word Burst for Reducing Address Bus Frequency.
Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz.
Available in 2.5 Clock Cycle Latency.
Two Input Clocks (K and K) for precise DDR Timing.
SRAM uses rising edges only.
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Sy.

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Published: Mar 14, 2017 |