CY7C1268KV18 Datasheet - Cypress Semiconductor

CY7C1268KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C1268KV18 Features

* 36-Mbit density (2 M × 18, 1 M × 36)

* 550 MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz

* Available in 2.5 clock cycle latency

* Two input clocks (K and K) for

Datasheet Details

CY7C1268KV18

Cypress Semiconductor

622.44 KB

36-mbit ddr ii+ sram two-word burst architecture.

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