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CY7C1268KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C1268KV18 Description

CY7C1268KV18/CY7C1270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture .

CY7C1268KV18 Features

* 36-Mbit density (2 M × 18, 1 M × 36)
* 550 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
* Available in 2.5 clock cycle latency
* Two input clocks (K and K) for

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Datasheet Details

Part number
CY7C1268KV18
Manufacturer
Cypress Semiconductor
File Size
622.44 KB
Datasheet
CY7C1268KV18-CypressSemiconductor.pdf
Description
36-Mbit DDR II+ SRAM Two-Word Burst Architecture

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📌 All Tags

36-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor
Cypress Semiconductor CY7C1268KV18-like datasheet