CY7C1292DV18 - (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture

Product Overview

Cypress Semiconductor

Part number	CY7C1292DV18
Manufacturer	Cypress Semiconductor
File Size	0.99 MB
Description	(CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
Datasheet	CY7C1292DV18 Datasheet
Additional preview pages of the CY7C1292DV18 datasheet.

The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

Separate Independent Read and Write data ports.
Supports concurrent transactions.
250-MHz clock for high bandwidth.
2-Word Burst on all accesses.
Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.

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Published: Oct 4, 2007 |