CY7C1294DV18, CY7C1292DV18 Datasheet - Cypress Semiconductor

CY7C1294DV18 (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture

The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs .

CY7C1294DV18 Features

* Separate Independent Read and Write data ports

* Supports concurrent transactions

* 250-MHz clock for high bandwidth

* 2-Word Burst on all accesses

* Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz

CY7C1292DV18_CypressSemiconductor.pdf

CY7C1294DV18 Datasheet Preview — This datasheet PDF includes multiple part numbers: CY7C1294DV18, CY7C1292DV18. Please refer to the document for exact specifications by model.

Datasheet Details

Part number:

CY7C1294DV18, CY7C1292DV18

Manufacturer:

Cypress Semiconductor

File Size:

0.99 MB

Description:

(cy7c1292dv18 / cy7c1294dv18) sram 2-word burst architecture.

Note:

This datasheet PDF includes multiple part numbers: CY7C1294DV18, CY7C1292DV18.
Please refer to the document for exact specifications by model.

CY7C1294DV18 Distributor

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TAGS

CY7C1294DV18 CY7C1292DV18 CY7C1292DV18 CY7C1294DV18 SRAM 2-Word Burst Architecture Cypress Semiconductor