* Separate independent read and write data ports
* Supports concurrent transactions
* 333 MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
CY7C1411KV18 Datasheet (1.28 MB)
CY7C1411KV18
Cypress Semiconductor
1.28 MB
36-mbit qdr ii sram four-word burst architecture.
CY7C1411KV18/CY7C1426KV18 CY7C1413KV18/CY7C1415KV18
36-Mbit QDR® II SRAM Four-Word Burst Architecture
36-Mbit QDR® II SRAM Four-Word Burst Architectu.
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