CY7C1513V18 Architecture Datasheet - Cypress Semiconductor

CY7C1513V18 Features

Architecture
Separate Independent Read and Write Data Ports
– Supports concurrent transactions
250-MHz Clock for High Bandwidth
4-Word Burst for reducin

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CY7C1513V18

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Cypress Semiconductor

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561.73kb

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📄 Datasheet

Description:

(cy7c15xxv18) sram 4-word burst architecture. The CY7C1511V18, CY7C1526V18, CY7C1513V18, and CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. Q

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Cypress Semiconductor

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