Datasheet4U Logo Datasheet4U.com

CY7C1373KV33, CY7C1371KV33 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

CY7C1373KV33 Description

CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 18-Mbit (512K × 36/1M × 18) Flow-Through SRAM with NoBL™ Architecture (With ECC) 18-Mbit (512K × 36/1M × 18) .

CY7C1373KV33 Features

* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
* Supports up to 133-MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin-compatible and functionally equivalent to ZBT™ devices
* Internally self-timed outp

📥 Download Datasheet

This datasheet PDF includes multiple part numbers: CY7C1373KV33, CY7C1371KV33. Please refer to the document for exact specifications by model.
datasheet Preview Page 2 datasheet Preview Page 3

Datasheet Details

Part number
CY7C1373KV33, CY7C1371KV33
Manufacturer
Cypress Semiconductor
File Size
0.96 MB
Datasheet
CY7C1371KV33-CypressSemiconductor.pdf
Description
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Note
This datasheet PDF includes multiple part numbers: CY7C1373KV33, CY7C1371KV33.
Please refer to the document for exact specifications by model.

📁 Related Datasheet

  • CY7C1373C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
  • CY7C1371S - 18-Mbit (512K x 36) Flow-Through SRAM (Cypress)
  • CY7C1372C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
  • CY7C1372CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)

📌 All Tags

Cypress Semiconductor CY7C1373KV33-like datasheet