CY7C1562XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Part number	CY7C1562XV18
Manufacturer	Cypress Semiconductor
File Size	1.20 MB
Description	72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
Datasheet	CY7C1562XV18-CypressSemiconductor.pdf

Separate independent read and write data ports.
Supports concurrent transactions.
450 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed syst.

📁 CY7C1562XV18 Similar Datasheet

CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)

Other Datasheets by Cypress Semiconductor

Published: Mar 14, 2017 |