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User’s Manual, V 0.1, Jan 2005 www.DataSheet4U.com XC800 Microcontroller Family Architecture and Instruction Set Microcontrollers N e v e r s t o

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CY7C1371C CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates

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CY7C1146V18 CY7C1157V18 CY7C1148V18 CY7C1150V18 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ ■ ■ ■ ■ ■ Functio

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CY7C1522KV18, CY7C1529KV18 CY7C1523KV18, CY7C1524KV18 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture 72-Mbit DDR II SIO SRAM 2-Word Burst Architec

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PRELIMINARY Am29F002NT/Am29F002NB 2 Megabit (262,144 x 8-Bit) CMOS 5.0 Volt-only, Sector Architecture Flash Memory DISTINCTIVE CHARACTERISTICS ■ 5.0

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CY7C2670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2

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( DataSheet : www.DataSheet4U.com ) CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture Feature

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CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit QDR™-II SRAM 2-Word Burst Architecture Features ■ Configurations CY7C1410JV18 – 4M x 8

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CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Features ■ Configurations CY7C1511JV18 – 8M x 8

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SPC584Cx, SPC58ECx SPC58 C Line - 32 bit Power Architecture automotive MCU Dual z4 cores 180 MHz, 4 MBytes Flash, HSM, ASIL-B Datasheet - production

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SPC584Cx, SPC58ECx SPC58 C Line - 32 bit Power Architecture automotive MCU Dual z4 cores 180 MHz, 4 MBytes Flash, HSM, ASIL-B Datasheet - production

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CY7C2663KV18/CY7C2665KV18 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Four-Word Burs

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CY7C1411KV18/CY7C1426KV18 CY7C1413KV18/CY7C1415KV18 36-Mbit QDR® II SRAM Four-Word Burst Architecture 36-Mbit QDR® II SRAM Four-Word Burst Architectu

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CY7C1168KV18/CY7C1170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit DDR II+ SRAM Two-Word Burst Architecture

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CY7C1319KV18/CY7C1321KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture 18-Mbit DDR II SRAM Four-Word Burst Architecture Features ■ 18-Mbit densit

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CY7C1370CV25 CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT™ • Su

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w w at .D w Features s s s s s s s U 4 t e e FAS216/216U/236/236U h aS Fast Architecture SCSI Processor Data Sheet s s s s s s s s s s m o .c QLo

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DPF1000 SERIES Dual output • • • • • • • • 1000W front end EN61000-3-2 compliant 11 x 6.0 x 5.0 inch size Hot pluggable N+1 redundancy Full set of sta

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CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Functional Descr

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CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Functional Descr

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