CY7C1419AV18 - 1.8V Synchronous Pipelined SRAM
CY7C1419AV18 Features
* 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
* 300-MHz clock for high bandwidth
* 4-Word burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz
* Two input clocks (K and K) for precise DDR t
