CY7C1911KV18 Datasheet - Cypress Semiconductor

CY7C1911KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture

CY7C1911KV18 Features

* Separate independent read and write data ports

* Supports concurrent transactions

* 333-MHz clock for high bandwidth

* Four-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz

Datasheet Details

CY7C1911KV18

Cypress Semiconductor

657.31 KB

18-mbit qdr ii sram four-word burst architecture.

📁 Related Datasheet

CY7C1911BV18 (CY7C1x1xBV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture (Cypress Semiconductor)

CY7C1911CV18 (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture (Cypress Semiconductor)

CY7C1911JV18 (CY7C1x1xJV18) 18-Mbit QDR II SRAM 4-Word Burst Architecture (Cypress Semiconductor)

CY7C1910BV18 1.8V Synchronous Pipelined SRAM (Cypress Semiconductor)

CY7C1916BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C1916CV18 (CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C1916JV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture (Cypress Semiconductor)

CY7C1916KV18 18-Mbit DDR II SRAM Two-Word Burst Architecture (Cypress Semiconductor)

TAGS

CY7C1911KV18 Distributor