CY7C1916BV18 - 18-Mbit DDR-II SRAM 2-Word Burst Architecture
The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture.
The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for Read and Write are latched on alternate ri
CY7C1916BV18 Features
* 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
* 300-MHz clock for high bandwidth
* 2-Word burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz
* Two input clocks (K and K) for precise DDR
