FDG6304P Datasheet - Fairchild Semiconductor

FDG6304P Dual P-Channel/ Digital FET

These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage a.

FDG6304P Features

* -25 V, -0.41 A continuous, -1.5 A peak. RDS(ON) = 1.1 Ω @ VGS= -4.5 V, RDS(ON) = 1.5 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 sur

FDG6304P Datasheet (227.14 KB)