ICS8752 Datasheet, Buffer, Renesas

ICS8752 Features

• Buffer
• Fully integrated PLL
• Eight LVCMOS outputs, 7Ω typical output impedance
• Selectable LVCMOS CLK0 or CLK1 inputs for redundant clock applications
• Inp

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ICS8752

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Renesas ↗

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📄 Datasheet

Description:

Lvcmos clock multiplier/zero delay buffer. The ICS8752 is a low voltage, low skew LVCMOS clock generator. With output frequencies up to 240MHz, the ICS8752 is targeted for high

ICS8752 Application

• Applications The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by the DIV_SELA0:

TAGS

ICS8752

Renesas

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